1. Field of the Invention
The invention relates to a digital logic gate and, more particularly, to a logic device with low electromagnetic interference (EMI).
2. Description of Related Art
Due to increasingly powerful functions of current electronic products, the associated circuitry is becoming more and more complicated. For a good electronic product, in addition to the inherent functions, an electromagnetic interference (EMI) has a key impact on the product quality and technical capability indication. Therefore, the EMI causes an essential problem in the design of electronic products. A circuit designer uses an advanced CAD tool to widen the capability of work in the design of electronic circuits, but to give the little help with the EMI problem.
A typical technology uses long channel of PMOS or NMOS transistors to reduce the transient current in a logic gate to thus reduce the EMI problem in the logic gate. However, such a long channel of transistor technology increases the cost due to the increased area required for the logic gate, which is caused by the increased channel length. In addition, when the process is changed, re-adjusting the channel length of a transistor is required, so as to increase the processing complexity. Another typical technology uses current-limited resistors to reduce the transient current of a logic gate. As shown in FIG. 1, one resistor 110 is added between the source of the PMOS transistor 120 and a high potential Vdd, and the other resistor 140 is added between the source of the NMOS transistor 130 and the ground.
In this case, the current-limited resistors 110, 140 can reduce the transient current. However, such a way can reduce the EMI in the logic gate but the area required for the logic gate is relatively increased. Therefore, it is desirable to provide an improved logic device to mitigate and/or obviate the aforementioned problems.